Time-Bomb HLS Trojan for Performance Degradation Payload

High-level synthesis (HLS) plays a pivotal role in the design of hardware intellectual property (IP) designs, especially from the domain of image/video processing, multimedia etc. However, backdoor hardware Trojans (HT) can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This paper presents a novel time-bomb triggering HLS Trojan with significant performance degradation (PD) payload. The proposed PD-HT can be covertly inserted in the mux-based interconnect design stage of HLS process and is stealthy/evasive by nature as it can be activated only through a specific rare-event triggering condition (by an attacker). Results and analysis revealed that the proposed HLS Trojan can cause significantly higher performance degradation (~ avg. 35 %) than prior HLS Trojan attack, at lower area overhead (avg.< 2.9 %).