SVM-Based Framework is Designed for Precise On-Chip Power Analysis in CMOS VLSI Circuits

Power analysis plays a crucial role in ensuring the reliability of very -large-scale integration (VLSI) circuits. Accurate power analysis is essential during the early stages of the design process to manage power budgets effectively and to implement strategies for reducing power consumption. One of the major challenges faced by the integrated circuit (IC) industry is addressing the increasing design complexity caused by growing process variations and reducing chip manufacturing turnaround time. Under these circumstances, estimating the average power consumption at higher design levels before chip fabrication becomes vital for optimizing designs and minimizing power usage. Traditionally, several methods have been developed to estimate power consumption. However, these conventional approaches are often time-consuming, resource- intensive, and rely heavily on manual processes, which makes them less efficient. Recently, machine learning techniques have gained significant attention in engineering applications due to their ability to model complex systems using historical data. These methods offer the potential for faster and more accurate predictions compared to traditional techniques. In this context, this study proposes a chip-based power estimation approach for complementary metal-oxide-semiconductor (CMOS) VLSI circuits using a support vector machine (SVM). The SVM model is designed to estimate power consumption dynamically during runtime. The effectiveness of the proposed model is evaluated based on key performance metrics, including power usage, delay, data accuracy, and error rate. This approach aims to provide a more efficient and automated solution for power estimation in VLSI circuits, addressing the limitations of conventional methods while improving overall reliability and design efficiency.