Comparative Analysis of Low-Power ICS Technique for CNTFET, FinFET, and CMOS Technologies

As the technology nodes shrink to below 20nm, the existing complementary metal oxide semiconductor (CMOS)-based circuit designs face substantial challenges like high power consumption, delay, and scalability. Beyond-CMOS emerging transistor device technologies like Carbon Nanotube Field-Effect Transistor (CNTFET) and Fin Field Effect Transistor (FinFET), are expected to encounter these limitations. In this paper, an inverter circuit is implemented using a low-power technique; Input Controlled Stacking (ICS). This technique dynamically regulates the active transistors count to reduce power dissipation without compromising the performance. The ICS-based design is evaluated using three different transistor device technologies i.e., CNTFET, FinFET, and CMOS. The circuits are simulated with PTM bulk CMOS BSIM4 22nm model, PTM-MG FinFET HP 20nm model, and Stanford 32nm CNTFET model, using Cadence Spectre and HSPICE tools. A comparison is made on key performance metrics like delay, power consumption, power-delay product (PDP) and energy-delay product (EDP). As per results, CNTFET-based inverter design consumes lowest power due to higher carrier mobility and ballistic transfer and FinFET shows reduced delay and improved scalability for lower nodes whereas CMOS exhibits higher power consumption and slow switching speed when compared to CNTFET and FinFET designs.