Synthesis of a reversible quantum Vedic multiplier on IBM quantum computers

Quantum computers provide considerable potential to enhance computing technology, anticipated to surpass conventional computers by resolving intricate challenges that existing systems cannot tackle. They use quantum algorithms for improved performance and depend on reversible computations based on quantum physics and linear algebra. In contrast to traditional computing, which may include irreversible processes, quantum computing relies on unitary operations that are fundamentally reversible. The parity-preserving feature enables the identification of both permanent and transient defects within circuits. The parity-preserving feature ensures that the input and output states are equal in reversible circuits. Vedic multipliers offer a crucial foundation in the design and implementation of digital circuits, recognized for their speed, efficiency, ease of calculations, reduction of errors, and broad applicability. Prior investigations of quantum Vedic multipliers have faced obstacles like elevated Quantum Cost (QC), substantial Garbage Output (GO), Constant Input (CI), augmented Gate Count (GC), and CNOT-V/V⁺ count, resulting in more resource use and implementation intricacy. These inefficiencies hinder the scalability and feasibility of quantum multipliers in high-performance computing applications. A proposed solution to these issues is to introduce a cost-effective, parity-preserving reversible quantum block synthesized through an established method that produces a network list of multi-controlled Toffoli (MCT) gates. This Toffoli-based network is then optimized using various techniques, ultimately transforming it into a network of fundamental quantum gates. This approach decreases quantum expenses, eliminates unnecessary outputs, and enhances quantum gate efficiency. Integrating this innovative technique into the reversible quantum Vedic multipliers offers a more efficient, cost-effective, and scalable solution than current approaches. All proposed designs, such as a half adder-subtractor, a ripple carry adder (RCA), and two-bit and four-bit Vedic multipliers, are suggested based on functional blocks and pre-existing components. The suggested structures undergo evaluation in comparison to existing state-of-the-art procedures, demonstrating their cost-effectiveness. The observed average savings for two-bit and four-bit Vedic multipliers, with respect to QC, number of CNOT-V/V⁺ count, GO, CI, and GC, are 20.01%, 19.38%, 37.51%, 37.51%, and 54.89%, and 22.71%, 18.78%, 27.23%, 31.10%, and 42.38%, respectively when compared to previous studies. Furthermore, all suggested circuits are evaluated and confirmed using the IBM quantum laboratory.