From MLIR to Scheduled CDFG: A Design Flow for Hardware Resource Estimation

Efficient early stages exploration in hardware design can significantly enhance design quality and reduce development time. This paper introduces a novel methodology that leverages the Multi-Level Intermediate Representation (MLIR) to extract Control and Data Flow Graphs (CDFGs) with earlystage resource estimates for area, delay, and power consumption. By employing Polygeist for C-to-MLIR conversion coupled with Graphviz for visualization, we generate structured CDFGs and then apply three scheduling algorithms: ASAP, ALAP, and Random. Evaluated through two case studies, our approach produces valid scheduled graphs and demonstrates how both code structure and scheduling strategy critically impact hardware resource utilization and performance. This work sets the stage for resource-aware design space exploration using MLIR, enabling designers to evaluate configurations and make informed tradeoffs prior to time-consuming synthesis processes.