A 96.5% Efficiency Hybrid Step-Up Converter With Low Input-Level Voltage Stress and Duty-Independent Constant Inductor Current

This article presents a duty-independent step-up converter (DIUC) for battery-powered or USB-powered devices. The DIUC limits the voltage stress on all switches to an input voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub>) level, eliminating the need for high-voltage (HV) transistors like LDMOS. Unlike previous step-up converters where the inductor current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_L </i>) rapidly increases as a duty (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>) rises, the DIUC maintains <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_L </i> equal to the load current regardless of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>. This feature mitigates the conduction loss due to the inductor parasitic dc resistance (DCR) and right-half-plane (RHP) zero effect, improving both power efficiency and frequency response. When changing the operation mode according to the conversion ratio (CR), the DIUC achieves a small overshoot of 158 mV and undershoot of 107 mV in the output voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub>) with the proposed smooth mode transition (SMT) technique. Additionally, a multi-step gate driving method with two precharging techniques reduces the required bootstrap capacitance by 46.3% to save the silicon area. The 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m prototype chip uses only 5-V CMOS transistors, while all bootstrap capacitors are integrated on the chip. With a 4.7-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>H inductor (DCR of 98 m<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula>) and two 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>F flying capacitors, the DIUC achieves high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} {_{\text {OUT}}}$</tex-math> </inline-formula> up to 13 V, a maximum load current of 1.2 A, and a peak efficiency of 96.5%.