HIL simulation of a solar PV-fed cascaded H-bridge multilevel inverter with AC-side battery storage and power management

The intermittent nature of solar power generation makes battery storage essential in standalone Solar Photovoltaic (SPV) systems. Typically, battery systems are placed on the direct current (DC) side, after the boost converter, to manage surplus or deficit power generated by the SPV system, using a Cascaded H-Bridge Multilevel Inverter (CHBMLI) topology. This paper proposes an alternative approach where a common battery bank is used on the alternating current (AC) side, instead of the DC side, to minimize the need for multiple controllers. A single bidirectional converter with a battery energy management system is implemented between the multilevel inverter and the AC side to regulate the AC output voltage while ensuring the load's power demand is met. The proposed SPV system, which includes voltage control via a cascaded H-bridge 7-level inverter and Maximum Power Point Tracking (MPPT), is implemented on a Field Programmable Gate Array (FPGA) using the Xilinx System Generator (XSG) for Hardware-in-the-Loop (HIL) simulations. The XSG automatically generates the VHDL code for sliding mode control, which is embedded in the FPGA. The Spartan 3E FPGA development board, along with the MATLAB/Simulink environment, is used for the HIL simulation.