Study of Temperature Dependence on DC/RF Parameters of Extended Channel Gate Stacked Heterojunction TFET

In this manuscript, a novel Hetero-junction TFET design is proposed, which utilizes a SiGe source and incorporates an extended section of the channel into the source region. This structure is further enhanced by the integration of an n+ pocket doping and a dielectric pocket (DP) at the drain-channel interface. The proposed structure is analyzed using the Sentaurus TCAD simulator in this study. The DP placed at the drain-channel junction depletes the drain region near the interface. This effectively increases the tunneling width at the drain-channel interface, resulting in a significant reduction of ambipolar conduction in the TFET. The suggested TFET reflects a better I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ratio of 2.79 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> and steeper SS of 10.52 mV/dec as well as mitigates ambipolar conduction in negative bias region. Furthermore, the impact of varying temperatures within the range of 300 K to 400 K on different parameters is analyzed. The device’s performance is critically dependent on temperature variation. The bandgap of the semiconductor material changes with temperature variation. The results indicates that the current conduction has minimal temperature dependency, while in ON state but shows a significant rise in OFF state current. Moreover, the study examines the consequences of temperature fluctuations on various analog/RF FOM parameters.