Analytical Modeling of the Ultra Short Channel Negative Capacitance Tunnel FET in Sub-Threshold Regime

This study explores the feasibility of utilizing a Negative Capacitance Double Gate Tunnel FET (NC-TFET) for energy-efficient digital logic implementations in the sub-threshold regime. A detailed analytical model for the drain current, incorporating the effects of band-to-band tunnelling (BTBT), has been developed and analyzed along with the subthreshold slope (SS). The optimized device demonstrates a notable ON current (~0.024 µA/µm at 250mV) and a Sub-threshold slope (SS) ranging between 12mV/dec and 22mV/dec while maintaining an extremely low OFF current (~fA/µm). The proposed model has been validated using SILVACO ATLAS and MATLAB simulations. This comprehensive analytical modelling suggests that NC-DGTFET is a promising candidate for energy-efficient digital logic circuit design in the subthreshold regime