Leveraging FPGA for k-Nearest Neighbours Classifier: Design and Performance Study

In the era of big data, real-time processing and fast decision-making are essential. The k-Nearest Neighbors (k-NN) algorithm, though effective, becomes computationally expensive on traditional CPUs, especially with large or high-dimensional datasets. Implementing k-NN on Field-Programmable Gate Arrays (FPGAs) offers a solution by leveraging parallel processing for accelerated computation. This work presents an in-depth analysis of FPGA-based k-NN implementation using HDL, comparing its performance with CPUs and GPUs. The results demonstrate significant improvements in speed and efficiency, highlighting the potential of FPGA-based acceleration in machine learning applications. This approach paves the way for scalable, high-performance classification in domains such as healthcare, finance, and e-commerce.