A 12-Bit 10-MS/s SAR ADC with 3-Bit Redundancy Capacitors

With the advancement of digital signal processing technologies and the evolution of CMOS processes, there is a growing demand for analog-to-digital converters (ADCs) with high energy efficiency, medium-to-high resolution, and compact area in biomedical devices. The successive approximation register analog-to-digital converter (SAR ADC) has gained widespread adoption due to its predominantly digital circuitry, where power consumption is primarily concentrated in the capacitor array, comparator, and SAR logic unit. Notably, the capacitor array accounts for over 60% of the total system power consumption, making it a critical optimization target. This paper presents a 12-bit SAR ADC implemented in TSMC 180nm CMOS technology. The design incorporates three redundancy capacitors and adopts a segmented capacitor architecture. Under a 1.8V supply voltage, with a sampling rate of 10MHz and an input signal frequency of 4.8MHz, the achieved signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 73.40dB and 77.21dB, respectively, while maintaining an effective number of bits (ENOB) of 11.9. The total power consumption is measured at 15.326µW.