Design of Power-Efficient High-Precision Dual-Mode Adder

This work presents the design and analysis of low-power arithmetic circuits optimized for approximate computing: the Power Efficient Single Exact Single Approximate (PESESA)-1 and PESESA-2 adders. PESESA-1 preserves exact CARRY calculation with approximate SUM with one error, whereas PESESA-2 approximates the CARRY with exact SUM calculation. The two designs operate in approximation mode for hardware and power efficiency and exact mode for highest accuracy with Power Gating (PG) for minimizing static power consumption. PESESA-1 and PESESA-2 are 34.2% and 25.6% more power-efficient than the mirror adder, respectively. Their efficient design makes them suitable for energy-constrained applications such as signal processing, data compression, and error-resilient computing. Their efficient design ensures a balance between computational accuracy, reduced power dissipation, and simplified circuit complexity, making them adaptable to a wide range of low-power applications.