Investigation of FinFET in terms of Device Design, Performance, and its Challenges

The paper provides an overview of the historical background, formation process, and operational mechanisms of FinFET. Overcoming the challenge of dimension scaling has been a consistent effort to fulfill the requirements of high-performance, high-density, low-power, and low-voltage intricate devices. Miniaturization serves as the primary catalyst for transitioning from microelectronic to nanoelectronic device structures. Planar CMOS scaling has consistently delivered improved performance and low-power devices at the forefront of technology nodes for more than three decades. The discussion also includes a review of various types of FinFETs, exploring diverse structures and materials to enhance performance. The paper delves into challenges encountered in FinFET development, such as corner effects (fin shape), parasitic capacitance and resistance, and fin patterning. Looking forward, a potential avenue to maximize FinFET's potential involves fostering the development and application of Gate-All-Around FETs (GAAFETs) based on FinFET technology.