Fracttional Order Single Balanced Mixer

This work presents a single balanced mixer topology in 32nm MOS node. The designing has been carried out using conventional and fractional capacitors of a certain fractional order, α. The Theory of fractional calculus has been used in this work to allow higher degree of freedom in circuit design. By analyzing the results, it has been seen that with increase in fractional order, α from 0.52 to 0.67 the peak voltage and current values in the waveforms increase by 25%, keeping all the other circuit parameters the same. Designing of fractional order capacitors (FOC’s) has been done using passive RC ladder structures. The coefficient values of the ladder for different fractional order, α have been determined using MATLAB programing. The novelty of this circuit is variation of mixing obtained by change in fractional orders and pseudo-capacitances employed. Higher fractional order and lower pseudo-capacitance results in greater mixing as has been observed in results of the paper. In comparison to integer topology the fractional version consumes greater power. An increase in power by 37.5% is attributed to the usage of successive parallel combinations of RC ladder circuits that have been used in circuit designing for fractional capacitors. An optimized circuit in terms of power can be obtained by utilizing CNTFET transistors in place of conventional MOS technology nodes.