Low-Power Multiplier-Less VLSI Design and Implementation of Linear Convolution Using Vedic Mathematics
We present in this paper on how we can replace the multipliers with basic operations like shifting and addition in the linear convolution method considering ease of implementation, making it ideal for low-power, resource-constrained environments, such as embedded systems and software-based applications. We have implemented the concept of vertical and crosswise multiplication procedure which is an ancient vedic multiplication process by replacing the multiplication property with shift and add operations. The proposed approach in this paper outperforms similar state-of-the-art research work in terms of power consumption as shown in comparative results.
Authors
- Sudip Ghosh (ORCID: https://orcid.org/0000-0001-5750-2501)
- Hafizur Rahaman (ORCID: https://orcid.org/0000-0001-9012-5437)
- Udisha Gangopadhyay
Institutions
- Indian Institute of Engineering Science and Technology, Shibpur (IN)
Publication Details
- Published
- 2025-04-05
- DOI
- https://doi.org/10.1109/devic63749.2025.11012393
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00