Low-power and High-speed CNTFET based Four-bit Static Approximate Modified Mirror Ripple Carry Adder for Image Processing

Several high-speed and low-power computing applications benefit from the approximate computing paradigm that promises a reduction in propagation delay and power consumption but at the same time produces a few erroneous outputs. In this work, an approximate full-adder circuit, which has been implemented by means of logic simplification, has been considered. It has been used to design a four-bit static approximate modified mirror ripple carry adder. The proposed circuit is simulated using 32 nm CNTFET devices on the Cadence Virtuoso tool, which delivers power of 22.47 nW, maximum propagation delay of 34.27 ps, PDP of 7.70 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-19</sup> J, and EDP of 26.39 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-30</sup> Js. Furthermore, to evaluate the effectiveness of this circuit for image processing applications, it has been tested for image sharpening. The output image exhibits a peak signal-to-noise ratio and structural similarity index of 29.88 dB and 0.91, respectively, which makes this approximate circuit ideal for image processing applications.