High Speed 16T DPTL Full Adder with Reduced Power Dissipation

This paper presents the design of a high-speed, low-noise Full Adder with reduced power dissipation using Differential Pass Transistor Logic (DPTL), which can be optimized for the integration into an n x n-bit multiplier. The proposed full adder circuit addresses critical requirements for high-speed operation, reduced power dissipation making it suitable for modern-generation digital systems where energy efficiency and high-speed arithmetic processing are essential. Differential Pass Transistor Logic (DPTL), as opposed to conventional CMOS logic, provides notable improvements in power, speed, and area, especially by leveraging NMOS-only configurations. These enhancements make DPTL a promising choice for arithmetic units in ALU (Arithmetic Logic Unit) and MAC (Multiply-Accumulate) operations. The proposed low time delay 16T DPTL Full Adder was designed in LTspiceXVII with CMOS 180nm bulk Technology. The proposed Full Adder has an Average Delay of 3.33 ns and a power dissipation of 5.32µW. The speed of the Full Adder is enhanced by 61% and the power dissipation is reduced by 25% compared to the existing design.