Impact of the Threshold Voltage Variability of the Junctionless MOSFET on Digital Performances in Sub-threshold Regime

The threshold voltage variability of Junctionless MOSFETs (JL-MOSFETs) significantly impacts digital circuit performance, especially in the sub-threshold regime. In this work, we analyze the statistical variations in threshold voltage due to process-induced factors such as channel doping fluctuations, gate work function variations, and oxide thickness non-uniformity. These variations lead to deviations in the sub-threshold swing, on-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>), and off-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>), affecting power consumption and switching reliability. Monte Carlo simulations are employed to quantify the impact on key digital performance metrics, including delay, noise margins, and energy efficiency. Results indicate that JL-MOSFETs exhibit lower variability compared to conventional inversion-mode transistors due to their bulk conduction mechanism. However, precise doping control is crucial to minimize degradation in performance. This study highlights the need for optimized device design and variability-aware circuit techniques to enhance JL-MOSFET reliability in ultra-low-power digital applications.