Design of Low Transistor Count Approximate Full Adder with Carry Approximation

In many digital signal processing (DSP) applications, such as image and speech processing, slight inaccuracies in output data are often tolerable for human interpretation. This may be exploited with approximate computing which allows for reduced computational complexity by using circuits that are intentionally designed to be less precise. By adopting approximate circuits, which require fewer transistors than their exact counterparts, designers can achieve more efficient hardware implementations. In this work, we explore a full adder design that leverages transmission gates to approximate the carry output using the primary inputs A and B. This approach effectively reduces the transistor count and propagation delay from the traditional 28T in accurate full adders to either 16T or 20T, depending on the level of approximation employed.