Design and Optimization of Dual-Source Vertical TFETs: Comparing Overlapped and Non-Overlapped Channel Architectures

This work presents the device-level design and performance analysis of Vertical Tunnel Field-Effect Transistors with Double Source (DS-VTFETs). Additionally, the study includes a comparison of two configurations: one with a channel overlap and the other without, highlighting their distinct performance characteristics. The introduction of a channel overlap is intended to enhance some specific device characteristics, leading to improved overall performance. The analysis shows that Dual Source Vertical Tunnel Field-Effect Transistors with overlapped structure depicts superior performance, achieving a high drive current (ION = 1.20 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> A/µm) improvement of approximately 21.32%, a reduction in off-state current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> = 3.95 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> A/µm) by 86.65%, a subthreshold slope (SS =11 mV/decade) improvement of 13.87%, and an average subthreshold slope (AVSS = 35.30 mV/decade ) improvement of 10.43% as compared to the non-overlapped structure. The technique used here provides more control over the electrical properties of the device. These findings highlight the potential of the overlapped DS-VTFET for achieving enhanced performance in current and subthreshold characteristics.