Design and Analysis of a High-Stability HS-12T SRAM Cell for Low-Power Applications

In this paper, the HS-12, a very stable 12T Static Random-Access Memory (SRAM) cell, is designed with better read operation. Traditional 6T SRAM cells suffer from major constraints, especially concerning read stability and power efficiency. To resolve these, the proposed 12T SRAM cell integrates extra transistors that practically separate read and write operations and thereby provide improved read, write, and hold stability. Critical performance indicators like read stability, write stability, power dissipation, and access times are comprehensively examined and contrasted with current SRAM architectures. Simulations with 45nm CMOS technology confirm that the HS-12T SRAM cell displays enhanced resistance to process, voltage, and temperature fluctuations, providing reliable operation under a wide range of conditions. Enhanced reading stability is especially beneficial for those applications with high reliability and low power requirements, like cache memory in handheld and embedded systems. This work offers a promising approach to future SRAM designs, providing an optimal balance between performance, energy efficiency, and robustness, and opens the door to future innovations in memory technology.