FPGA-based Hardware Acceleration of Scalable Convolutional Layers for Deep Learning Inference

Deep learning inference demands high computational efficiency and scalability, which traditional architectures struggle to provide. To address this, we propose an FPGA-accelerated scalable convolutional neural network (CNN) architecture optimized for inference. The design leverages FPGA’s parallelism and reconfigurability, integrating convolution, activation, and reshaping operations. It sequentially processes input data, synchronizing layers via control signals. The convolutional layer extracts spatial features, reshapes the feature map, and passes it to fully connected layers, with the output layer generating class probabilities. Our FPGA implementation achieves a remarkable 63000x speedup over CPU-based inference and a 6000x improvement compared to GPU-based inference with significantly reduced resource (except IO) requirements.