Exploring CMOS Technology Impact on Static Random Access Memory (SRAM): A Performance Assessment

SRAM is a volatile memory having faster access than DRAM, used for caching and internal registers. Researchers using lower nano-scale CMOS technologies struggle to construct a low-power, low-noise, and area-efficient SRAM. This study evaluates SRAM cell structures in 16nm, 22nm, and 32nm CMOS technology based on average power consumption, propagation delay time (PDT), static noise margin (SNM), total energy, and power delay product (PDP). The simulations, utilizing a 0.7V power source, demonstrated that SRAM 7T employing 22nm CMOS technology exhibited notable evaluation in terms of average power and energy efficiency, registering values of 5.999μW and 599.9fJ, respectively. Meanwhile, SRAM 9T with 32nm CMOS technology displayed outstanding performance in propagation delay for Write-0 and Read-0 operations. Notably, SRAM 8T with 32nm and SRAM 7T with 16nm CMOS technology showcased remarkable SNM values. Overall, the 32nm CMOS technology demonstrated the most promising results. This assessment employed Cadence Virtuoso Tools for simulations and meticulous data analysis.