ASIC Design of an Interval Type-2 Fuzzy Logic Engine for Control Application

Despite the existence of VLSI engines for inference generation using type-1 fuzzy sets, little is known about (interval) type-2 fuzzy VLSI engines. An ASIC-based type-2 fuzzy inference engine that was created in two stages is presented in this work. A traditional state-machine method is used in the first stage to construct the control logic and dataflow pathways. In order to verify time restrictions and enhance circuit performance, the inference engine is synthesized on an FPGA in the second stage. Synopsys Design Compiler is used to realize the final hardware implementation. When compared to current implementations, the suggested design performs better in terms of processing speed, resource usage, and inference accuracy. Our method overcomes the drawbacks of current type-1 fuzzy hardware and provides a scalable and effective solution for real-time fuzzy inference applications.