Numerical Simulation for Analog Performance Assessment of Vertically Stacked FeFinFET

This paper explores the impact of localized charges on the analog performance of Vertically Stacked Ferroelectric FinFET (VS-FeFinFET), integrating advanced technologies like SOI, strained tri-layered channel, and ferroelectric material for improved gate control. It examines how interfacial trap charges (ITCs), induced by radiation or stress, affect device performance. VS-FeFinFET shows improvement in leakage current (Ioff) by 53.1%, switching ratio by 105%, and threshold voltage (Vth) by 9.31% along with significant enhancement in other performance parameters for negative ITCs. By varying ITC’s densities (1 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> -1 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–2</sup>), the study reveals that multifold reduction in Ioff leds to boost in switching ratio by 350% and 1.55 times in Vth with increasing density. These insights aid in optimizing VS-FeFinFET for enhanced reliability and efficiency, shaping next-generation electronics.