CNT-based charge pump with linearly distributed capacitance for rising time improvement

The demand for energy-efficient, high-speed, and low-power on-chip voltage generation using next-generation devices is crucial in modern integrated systems. In this work, a four-stage cross-coupled CP is designed using Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed CP employs a linearly distributed capacitance strategy to enhance rise time and energy efficiency. The slope parameter, a, which ranged from 0 to -0.8, is assessed by simulations utilizing the 32 nm CNTFET model in Cadence Virtuoso. Initially, the results show that CP with a = -0.8 achieves the shortest rise time (2.81μs) and lowest energy consumption (4.90 pJ) at a total capacitance, C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>, of 10 pF and C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf>/C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> of 0.01, with C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> the equivalent load capacitance. The proposed CNTFET-based linearly distributed four-stage CP is expected to be employed in non-volatile memory (NVM), and compute-in-memory (CIM) applications.