Reliability Study of Differential Flip-Flops with Static Contention-Free Characteristics and Redundant Transition-Free Change Sensing for Low-Power Applications

This study explores the performance and reliability of Differential Flip-Flops (FFs) with contention-free static characteristics & redundant transition-free Change sensing for future low-power & low-voltage applications. The circuit is designed with 16 nm CMOS technology with 0.7 V of power supply (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>). We also studied the temperature (T) effect on the behavior of this differential FF with redundant transition-free characteristics. On top fit, we analyzed the performance of this FF in terms of power & delay. In addition to it, we examined the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> scaling effects on this flip-flop performance by changing the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> from 0.7 V to 1.2 V. Finally, we also explored the influence of transistor size downscaling on the D flip-flop performance and this work is carried out using SPICE tools. This flip flop is emerged as a key technology for future internet of things (IoT) Applications.