Optimized Decoupling Capacitor Estimation and Allocation for Supply Noise Reduction in SoC using Soft Computing and Machine Learning Techniques

In today’s VLSI design, the number of transistors has increased significantly. Implementing an efficient PDN is becoming a difficult issue with very high packing density designs. With ultra-high switching frequencies also contributes to variation of voltages in the electrical nodes, which contributes to supply noise. This noise voltage may result in malfunctioning of the integrated circuit. Therefore, reduction of supply noise is a major concern in system-on-chip. In this work PSN has been optimized using decoupling capacitors. The decap has been optimized using SOS and KNN algorithms. Finally, the integrated circuit has been portioned using pruning technique, floor planning using PSO algorithm and routing has been done using TSP algorithm. Simulation results show there has been overall improvement in the performance of the test circuits.