8-Bit Approximate Multiplier using Approximate Full Adder

Approximate computing has gained significant attention in recent years due to its ability to trade computational accuracy for improvements in power, area, and speed. This paper presents three novel approximate full adders used in the Wallace multiplier, aimed at error-resilient applications such as image processing and machine learning. The proposed designs are evaluated for key performance metrics, including power consumption and error rate, using hardware simulations. Comparative analysis with existing approximate multipliers demonstrates the effectiveness of the proposed design in achieving a balance between accuracy and hardware efficiency. This work exhibits improved accuracy with a Mean Error Distance (MED) of 30.62 in all the proposed designs, compared to previous low power design (EAFA2) with an MED of approximately 156.17. Additionally, DAFA3 achieves a 41% power reduction compared to an exact full adder.