Novel Design Techniques for Energy-Efficient Double-Tail Dynamic Comparators

This study explores various dynamic comparator and Double-Tail comparator by examining their delay and power characteristics to enhance operational speed. A lot of high-speed ADCs, such flash ADCs, need comparators with tiny chip areas, low power consumption, and high speed. Both the proposed dynamic comparator and the double-tail comparator utilize positive feedback mechanisms to convert analog inputs into fully digital outputs. In order to achieve power efficiency and great speed, designed comparators are proposed by altering low voltage low power comparators circuits action. Within the suggested comparators, system's power consumption and delay period would both be considerably decreased. The simulations are executed in proprietary Custom compiler, H-Spice 14nm FinFET and 32nm CMOS technologies with 1.2V supply voltage. Power consumption of double-tail dynamic comparator (DTDC) is 1.828µW for 32nm and 9.131µW for 14nm. Power and delay has been reduced by using same area as the existing literature. In contrast utilising the comparator with two tails for the suggested comparator for both power usage and wait times have been substantially decreased.