Design of Approximate Multipliers Using Leading Zero/One Detector

In power-constrained applications like AI, video processing, and embedded systems, energy-efficient hardware is vital. This paper proposes two novel approximate multiplier designs leveraging Leading Zero/One Detector (LZ/OD) circuits implemented on FPGA. Our OptLZOD design introduces an optimized LZ/OD circuit that reduces power consumption by 2.19% compared to LOZD and 41.76% compared to HLR_BM_2. Our R8LZOD design incorporates a radix-8 booth multiplier achieving 1.09%, 37.7%, and 46.2% improvement in Power-Delay Product (PDP) over LOZD, HLR_BM_2, and DURM6_16 respectively. Both designs dynamically adjust bit-width by detecting leading zeros/ones, minimizing energy usage while maintaining acceptable error metrics. These implementations offer compelling solutions for high-speed, low-power applications with minimal performance compromises, demonstrating the efficacy of our approach for energy-efficient hardware design.