Comparative Analysis of XOR Implementation using CMOS Logic, Domino Logic - Keeper Technique

As technology continues to scale and advance, achieving the primary goals of design i.e., low power consumption and faster circuitry have become more feasible. The continuous advancement of technology scaling enables significant reductions in power consumption, a critical objective in digital logic design. Power consumption in digital circuits primarily depends on factors such as supply voltage, the number of transistors used, and transistor scaling. While CMOS technology predominantly relies on inversion logic using NAND and NOR structures, alternative logic design methodologies can optimize transistor usage. Traditional XOR gate designs require multiple transistors; however, this paper presents methodologies for 2-input XOR and 4-input XOR gate implementations using CMOS logic, Domino logic (Keeper Technique) in 90nm technology. The proposed Domino Logic design achieves reduced power consumption compared to conventional CMOS XOR implementations.