FPGA Implementation of Transposed FIR Filter for De-Noising ECG Signals

An Electrocardiogram (ECG) is a bioelectrical signal that represents the heart's condition by capturing its potential changes. It is a commonly used technique for the early detection and assessment of cardiovascular disease (CVD). However, various types of noise can interfere with the ECG signal during recording, potentially leading to an inaccurate diagnosis. This paper describes the design of an effective ECG denoising method implemented in an FPGA. The design is realized with a transposed FIR filter based on a Vedic multiplier and a Carry Select Adder (CSA) and implemented on an FPGA. FPGAs are reconfigurable and reprogrammable in nature and hence are the best choice for such applications. The transposed FIR filter is chosen for its linear phase response and design flexibility, making it highly suitable for high-performance applications with minimal resource utilization. The proposed design incorporates a high-speed multiplier-accumulator unit and utilizes on-chip memory for rapid access to filter coefficients, significantly enhancing computational efficiency. Simulations and synthesis were performed using MATLAB and Vivado 2022.2. The results demonstrate a substantial improvement in the signal-to-noise ratio (SNR) and a significant reduction in artifacts, leading to clearer and more accurate ECG signal interpretation. The proposed filter achieves lower power consumption, reduced latency, and improved operational efficiency, making it ideal for real-time ECG monitoring.