Low-PDP 7:3-Counter with Novel Multi-threshold 2:1-Multiplexer

Current endeavour unfolds a clever design strategy to achieve low-PDP 7:3-counter using novel multi-threshold 2:1-Multiplexer for efficient multiplication. The idea is verified by constructing gate-level circuit with DSCH3.1 first and corresponding transistor-level circuit is designed next on 45nm PDK with BSIM4 technology parameters using Tanner EDA S-Edit. The 1100m-V is the main supply for the design and is excited with every possible custom bit-pattern using v-bit input source of Tanner-EDA to validate. The layout of proposed counter is constructed with 45-nm SPDM CMOS process technology and is evaluated through post-layout transient simulation in all three design corner (i.e. TT, SS and FF) applying 10k random test-patterns at room temperature. The PDP (Power-Delay-Product) is the crucial FOM for digital circuit and that has been measured and benchmarked with some recent competitive designs under same sets of test-pattern@125MHz data rate and in identical operating environment.