Design of High Performance Scan D-Flipflop Using TIGFET

A new power-efficient Scan D flip-flop is proposed using a novel transistor architecture, the Three-Independent- Gate Field Effect Transistor (TIGFET), leveraging TIGFET-10nm technology, that offers its advantage of improved controllability through multiple independent gates. Conventionally the Scan DFF is implemented using FIN- FET technology. But as the size is reduced the leakage current increases, increasing the power consumption. A delay of 100ns is seen in the DFF implemented by FINFET technology. The increased controllability and higher switching rate of TIGFET helps in reducing the leakage current and delay. Thus the TIGFET-based Scan D flip-flop is expected to have power consumption reduced by 77% and transistor count as well as area reduced without compromising on the performance, which makes it an ideal fit for any advanced high-speed low-power digital system. Thus, the benefit of multi-gate control in TIGFETs is taken in this current design to reduce dynamic power consumption yet allow flexible scan enablement needed for DFT applications. The power-delay-area improvements are confirmed through SPICE simulation using Synopsys HSPICE Tool, which establishes TIGFET as a promising candidate for future VLSI technology.