Design of Underlap PDSOI FinFET-Based Capacitorless 1T-DRAM with High-K Spacers for Enhanced Performance

This work presents the design and simulation of an Underlap PDSOI FinFET based Capacitorless 1T-DRAM with spacers using TCAD simulation tools. In the proposed device, the PDSOI and channel regions of the FinFET act as a floating region, which stores holes for use in the Capacitorless 1T-DRAM application. These holes are primarily generated through high-impact ionization occurring at the channel-drain junction. The PDSOI region is surrounded by a low-k isolation dielectric oxide, providing isolation between the active regions and reducing capacitive coupling between the PDSOI region and the gate electrode. This reduction in coupling improves the device sensing margin. High-k spacers are also used adjacent to gate electrode to reduce the leakage and enhance the retention of the device. By utilizing a single transistor for the DRAM, the complexity of the device is reduced, allowing for higher DRAM density in integrated circuits, which boosts productivity. The proposed device also offers several advantages, including low fabrication costs, low power consumption, a high sensing margin (~132 μA), long retention time (> 1 ms), and fast read/write operations (~10 ns).