Optimizing Power Consumption: CSD-Based 16-Bit Multiplier for Low-Power Systems

This work introduces a new design of a 16-bit multiplier based on a Canonical Signed Digit (CSD) representation, optimized for low-power implementations. The design reduces switching activity by a great extent, which leads to a significant 99.4% power saving when compared to traditional Vedic multipliers. Reducing the number of non-zero bits in the CSD representation minimizes the number of partial products, which leads to reduced dynamic power consumption. Experimental results prove that the design reduces delay by 82%, with a competitive slice utilization. This work sets a new standard for energy-efficient multipliers, and it is suitable for resource-limited systems like IoT devices and real-time DSP applications.