RFCNet: A Novel Approach for Wafer Map Defect Classification Based on Residual Learning Using Autoencoder-Based Data Balancing
Accurate classification of wafer map defects is essential for improving semiconductor manufacturing processes and reducing costs. However, class imbalance in defect datasets poses a significant challenge, leading to biased models to majority classes and reduced performance on minority defect classes. In this study, we propose an autoencoder-driven lightweight Residual Fully Convolution Network (RFCNet), a novel pipeline that integrates data balancing with a robust classification framework to address these issues. The pipeline consists of three key components: preprocessing using one-hot encoding for spatial defect representation, an autoencoder for data augmentation to balance class distributions, and a residual Fully Convolutional Neural Network (FCNN) for multiclass classification. Our autoencoder generates synthetic samples by adding controlled noise to the latent space, creating diverse yet realistic wafer map data. The residual FCNN leverages hierarchical feature extraction and multi-scale learning to classify defects across eight classes. Despite its effectiveness, our model is lightweight with a total of 257k parameters, making it computationally efficient. We evaluated RFCNet on the predefined test set of the WM-811K dataset, achieved an accuracy of 98.61%, outperforming existing approaches. RFCNet addresses critical challenges in wafer defect classification by combining effective data balancing and robust feature extraction. The model’s ability to handle underrepresented classes further highlights its robustness and practicality. This work demonstrates significant potential for improving defect classification in industrial semiconductor applications and sets the foundation for future research.
Authors
- Priyanti Paul Tumpa (ORCID: https://orcid.org/0000-0002-9110-714X)
- Md. Saiful Islam (ORCID: https://orcid.org/0000-0003-2997-6579)
- M Uddin (ORCID: https://orcid.org/0000-0001-6210-0814)
Institutions
- Chittagong University of Engineering & Technology (BD)
Publication Details
- Published
- 2025-02-13
- DOI
- https://doi.org/10.1109/ecce64574.2025.11013081
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00