Parity based Error Correction Code for Embedded Memories

Modern technology is rapidly evolving; modern circuits are becoming more optimized and complex, enabling higher processing speeds and increased storage capacities. However, as electronic devices shrink in size, they become more susceptible to faults, particularly in radiation-intensive environments and extreme temperatures. One major concern in memory systems in modern technology is the data corruption caused by charged particles, which are leading to transient faults that affect system reliability. In this work, a novel Error Correction Code (ECC) method has been introduced, specifically the parity-based ECC, which has a high rate of detecting and correcting the burst errors. This design was implemented using Verilog and synthesized using the Cadence tool on a 45-nm technology node. The proposed ECC can correct up to 4-bit adjacent and non-adjacent errors for 16-bit data and 8-bit adjacent and non-adjacent errors for 32-bit data. The experimental results showed that the error correction code corrects 100% of quadruple adjacent error and 8-bit adjacent error bits. In addition, the area and power consumption as shown considerable reduction when compared to two other existing works.