Design of a Pipelined High-Speed Analog-to-Digital Converter

In this paper, a four-stage pipelined high-speed analog-to-digital converter (ADC) is proposed to meet the application requirements of domestic high-speed and highprecision ADC in the aerospace field. The designed ADC adopts switch bootstrapping technology, ring oscillator amplification technology and sampling network timing calibration technology, breaking through the bottleneck of the mutual exclusion between speed and power consumption of traditional pipelined ADCs. The test results show that the designed 14-bit ADC can achieve a sampling rate of 1 Gsps. When the oversampling rate (OSR) = 1, the signal-to-noise and distortion ratio (SNDR) = 65.2 dB, the effective number of bits (ENOB) = 10.5 bits, the spurious-free dynamic range (SFDR) is greater than 80 dB, and it has a timing adjustment accuracy of 2 ps and a timing adjustment range of 60 ps, providing technical support for the subsequent engineering development of domestic high-speed and high-precision ADC chips.