Comparison and Analysis of Dynamic Comparator Using LECTOR and GALEOR Techniques with 180nm and 45nm Technologies

This paper introduces a low-power dynamic CMOS comparator designed using 45nm and 180nm technology, which operates at different voltages. To achieve optimal performance, we employ novel circuit design techniques such as the LECTOR (Leakage Control Transistor) and GALEOR(Gate Leakage Transistor). By incorporating leakage-control transistors within the active-high (PUP) and active-low (PDN) networks, we eliminate critical paths and significantly reduce leakage current compared to traditional designs. Our approach leverages the principle of multiple transistors off-states to minimize power consumption. The proposed comparator is evaluated in terms of power dissipation and delay, demonstrating substantial improvements over existing solutions. This paper analyzes the designs of LECTOR and GALEOR comparators, both of which provide significant advantages in power and delay optimization. LECTOR achieves a balanced improvement by reducing power consumption by 13-23% while maintaining efficient delay performance, particularly at higher voltage levels. On the other hand, GALEOR excels in power efficiency, offering remarkable savings of over 96%, making it highly suitable for ultra-low-power applications. Together, these designs present versatile solutions that enhance efficiency in modern electronic systems, catering to various needs in power-sensitive and performance-driven applications.