A Compact Broadband On-Chip True-Time Delay Design Based on Cascaded T-Coil Structure

This article presents an innovative design method aimed at achieving a compact broadband true-time-delay (TTD) using the T-coil cascade approach. The proposed method utilizes matrix analysis to approximate the LC equivalent of transmission lines (TLs) and derives closed-form equations for T-coil circuit components. This method combines high-frequency parasitic parameters with interstage coil coupling to enhance accuracy. It employs sequential cascading technology to improve isolation between T-shaped coils and minimize circuit area. To demonstrate the effectiveness of this method, a real-time delay circuit comprising four delay units (13.5, 27, 54, and 108 ps) was implemented using a 45-nm CMOS process. The measurement results confirmed the design’s performance within the frequency range of 10–30 GHz: the overall insertion loss of the TTD circuit is better than −13.04 dB, the return loss is less than −10.4 dB, and the chip area measures just <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$824 \times 500 \mu \text {m}$</tex-math> </inline-formula>. The figure of merit (FoM) of this work has achieved the best results recorded to date.