Design and Evaluation of a Low-Power Novel NMOS-Based Adiabatic Circuit

This paper presents a comprehensive study of innovative low-power logic gate designs, including Inverter, NAND, NOR, and XOR-XNOR, aimed at enhancing energy efficiency in digital circuits. By employing transient analysis using LTSpice software, the proposed designs are compared with existing technologies such as ECRL, 2n2n2p, PFAL, IPFAL, and 2P-PFAL across various frequencies (0 MHz, 25 MHz, 50 MHz, 100 MHz, and 200 MHz) and input voltages (0.9V and 1V). The results demonstrate that the proposed circuits consistently exhibit lower power consumption, with significant reductions noted particularly at higher frequencies. For instance, the proposed Inverter consumes only 50.976 nW at 1V and 200 MHz, while existing technologies consume considerably more power. Similarly, the proposed NAND and NOR gates also show remarkable efficiency. This work highlights the potential of the proposed logic gate designs to meet the growing demand for energy-efficient electronic components, making them suitable for modern applications in the realm of sustainable and low-power electronics. The findings contribute valuable insights for future research in circuit design and energy conservation technologies.