A Multi-Stage Common Source Cascode LNA Design Using 90-nm CMOS Technology

This paper presents a Low Noise Amplifier (LNA) design that uses 90-nm CMOS technology and is optimized for wideband (3.2-4.4 GHz) wireless communication applications. This Multi-stage design of the suggested LNA architecture uses multiple (two) common-source (CS) cascode topologies to reduce noise and increase gain, while the first stage uses a common-gate (CG) transistor configuration to guarantee efficient wideband input impedance matching. With crucial metrics like an input reflection coefficient (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf>), reverse isolation (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</inf>) that was found below -10 dB for 3.2-4.4 GHz, in which our focusing frequency is 3.54 GHz. Forward gain (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</inf>) was found within the range above 10 dB for the design of an effective LNA, which was simulated using the Cadence Virtuoso environment, and exhibits superior performance. Excellent output matching was shown by the output reflection coefficient (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</inf>), which was also found below -10 dB, which is also a requirement for good performance. Furthermore, the LNA attains a low noise figure of 2.97 dB, which makes it ideal for contemporary wideband applications where excellent linearity and low noise are essential. The circuit is inexpensive and suitable for integration into large-scale systems because of its simplicity, low component count, and utilization of 90-nm CMOS technology. This design is basically gain-performance based and it balances the trade-offs of noise, gain, and stability, providing a potential solution for next-generation wideband wireless communication receivers.