Design, Implementation and Verification of Five Stage Pipeline RISC-V Core (RV32I ISA)

RISC-V has earned popularity in designing modern computing devices because of its open architecture availability, modularity, extensibility, security, and royalty-free licenses. RISC-V architecture has paved the way of learning and designing processors for students and small companies. While there are existing implementations of RISC-V processors, none are intuitive enough for a beginner to follow. The aim is to build a RISC-V processor that is easily scalable, easy for beginners to learn, and lightweight enough to be implemented on even small FPGAs. In this paper, a 32-bit RISC-V pipeline core has been designed with the System Verilog programming language. The processor includes a basic five stage pipelining and uses Harvard architecture for memory. The barebone nature of the design allows for a lot of potential for upgradability. After analyzing the RV32I instruction set, the core has been verified both on the Field Programmable Gate Array (FPGA) platforms (DE2-115) and online Electronic Design Automation (EDA) playground tool to make it accessible for everyone. Synthesis has been conducted for the DE2-115 FPGA board. Finally, the core has been compared to other beginner-friendly cores from existing literature.The core proposed here demonstrates an highly efficient, low power, and medium performance implementation for small and mid-range FPGA boards.