Hardware Acceleration of Scalable Artificial Neural Network Inference on FPGA

Artificial intelligence (AI) relies on tasks like pattern recognition and object detection, but software-based implementations often struggle to meet real-time requirements. Field-Programmable Gate Arrays (FPGAs) have become a promising solution for hardware acceleration, offering parallelism, energy efficiency, and adaptability, making them ideal for accelerating Artificial Neural Networks (ANNs) in edge and low-power environments. This paper implements a scalable and efficient FPGA-based ANN inference model, incorporating a fully connected layer with sigmoid activation for non-linear processing. The design is evaluated for FPGA resource utilization and benchmarked against CPU and GPU implementations for computational time. Results show that the FPGA implementation achieves a 34,000x speedup over CPU-based inference and a 2,000x improvement over GPUs on computational time while consuming significantly fewer resources on FPGA (except IO).