An Analytical Device Model for Vertical Channel-All-Around InGaZnO Thin-Film Transistors

Vertical channel-all-around (CAA) thin-film transistors (TFTs) based on amorphous InGaZnO (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</i>-IGZO) show significant potential for innovative dynamic random access memory (DRAM) integration within back-end-of-line (BEOL) CMOS. Despite this promise, device models for vertical CAA architectures remain limited or virtually unavailable. In this work, we present an analytical device model for vertical CAA-TFTs, developed to capture the interplay between free carriers, tail states, and deep electronic states in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</i>-IGZO. Analytical expressions for surface potential, capacitance, and drain current are derived and validated through comparisons with experimental data and numerical simulations. This study provides valuable insights for developing circuit simulators for BEOL integration applications using vertical CAA-TFTs.