Successive Probability Approach for 1-Bit Quantization Ising Computer Demonstrated With 8×2 Spin Orbit Torque P-Bits Array

The extreme 1-bit quantization Ising computer proposed in our previous work lowers the requirement of spin orbit torque (SOT) probabilistic bit (P-Bit) devices and corresponding digital-to-analog converter (DAC) required by writing circuits. However, its ability to address complex problems remains limited, as 1-bit quantization restricts the coupling strength in Ising computation to only two discrete quantization points. In this work, we further proposed successive probability approach which can be easily implemented with nonideal P-Bit devices in the framework of 1-bit quantization. During the sampling stage of Ising computation, this approach achieves multibit sampling capability by leveraging the combination of two consecutive probabilistic switches. It is experimentally demonstrated with the <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</roman> × <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</roman> P-Bits array that XOR logic gate and integer factorization are accurately solved by successive probability approach. Reinforced by this novel successive probability approach, the 1-bit quantization Ising computer becomes a promising general-purpose hardware implementation for Ising computation to solve various combinatorial optimization problems.