Manufacturing Challenges of Hybrid Bonding for Chiplets Heterogenerous Integration

Abstract Hybrid bonding is an important interconnect technology for heterogeneous integration. As the wafer-to-wafer hybrid bonding is extending toward chip-to-wafer bonding for better yield and versatility of chiplets integration, various issues have been raised on top of those for wafer-to-wafer hybrid bonding. A few key applications to be potentially benefited by high density chip-to-wafer hybrid bonding are first overviewed. Progress would not have been made without the great support of the industry at all levels, but manufacturing challenges are yet to be overcome as addressed by a few examples in this overview. These challenges include but not limited to establishing package platforms up to 3.5D package, fabricating hybrid bonded integrated chiplets from mixed nodes and different foundries by manufacturers, enabling high accuracy bonding overlay and reticle stitching, upgrading equipment for bonding thin chiplets, developing materials and processing technology to support lateral expansion of interposer size and vertical expansion of the multilayer stacking, and improving the understanding of hybrid bonding mechanisms impacted by various dielectric materials and surface activation processes. Nevertheless, the system technology co-optimization should always be conducted to minimize the warpage, reduce thermal impacts, and achieve the desired yield and reliability lifetime.