Transforming Synthesized Netlists into a Feasible & Compliant Functional Bookshelf Format

This paper presents a software tool that converts synthesized Verilog netlists into comparable Bookshelf Format, a widely used format pertaining to physical design research.While the de facto industry standard LEF/DEF Format provides detailed technology-specific information, it includes additional data that might be irrelevant in particular research fields, e.g.development of 2D placement algorithms.The Bookshelf Format simplifies any such process by including only essential details.The tool described in this work extracts the aforementioned data and generates the appropriate files.An overview of the architecture and key-points of the implementation are presented along with performance metrics to show its efficiency.The results indicate that the tool scales well with design complexity, making it suitable for generating benchmarks regardless of their size.

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Publication Details

Published
2024-12-13
DOI
https://doi.org/10.1145/3716554.3716573
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Transforming Synthesized Netlists into a Feasible & Compliant Functional Bookshelf Format

Athanasios Kakarountas, Antonios N. Dadaliaris, George D. Stamoulis, George K. Kranas et al.
VLSI and Analog Circuit Testing
article

Transforming Synthesized Netlists into a Feasible & Compliant Functional Bookshelf Format

Athanasios Kakarountas, Antonios N. Dadaliaris, George D. Stamoulis, George K. Kranas, Kosmas Kariotis
article en

Abstract

This paper presents a software tool that converts synthesized Verilog netlists into comparable Bookshelf Format, a widely used format pertaining to physical design research.While the de facto industry standard LEF/DEF Format provides detailed technology-specific information, it includes additional data that might be irrelevant in particular research fields, e.g.development of 2D placement algorithms.The Bookshelf Format simplifies any such process by including only essential details.The tool described in this work extracts the aforementioned data and generates the appropriate files.An overview of the architecture and key-points of the implementation are presented along with performance metrics to show its efficiency.The results indicate that the tool scales well with design complexity, making it suitable for generating benchmarks regardless of their size.

University of Thessaly (GR)
Quality Education
Openalex Percentile: Top 66%
VLSI and Analog Circuit Testing
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