Transforming Synthesized Netlists into a Feasible & Compliant Functional Bookshelf Format
This paper presents a software tool that converts synthesized Verilog netlists into comparable Bookshelf Format, a widely used format pertaining to physical design research.While the de facto industry standard LEF/DEF Format provides detailed technology-specific information, it includes additional data that might be irrelevant in particular research fields, e.g.development of 2D placement algorithms.The Bookshelf Format simplifies any such process by including only essential details.The tool described in this work extracts the aforementioned data and generates the appropriate files.An overview of the architecture and key-points of the implementation are presented along with performance metrics to show its efficiency.The results indicate that the tool scales well with design complexity, making it suitable for generating benchmarks regardless of their size.
Authors
- Athanasios Kakarountas (ORCID: https://orcid.org/0000-0001-5431-2454)
- Antonios N. Dadaliaris (ORCID: https://orcid.org/0000-0003-0777-6867)
- George D. Stamoulis
- George K. Kranas (ORCID: https://orcid.org/0000-0003-3864-8059)
- Kosmas Kariotis
Institutions
- University of Thessaly (GR)
Publication Details
- Published
- 2024-12-13
- DOI
- https://doi.org/10.1145/3716554.3716573
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00